1. Field of Invention
The present invention relates to a phase locked loop (PLL). More particularly, the present invention relates to a PLL employing a plurality of phase frequency detectors (PFDs) and charge pumps (CPs) to accomplish fractional frequency division.
2. Description of Related Art
In communication systems or computer systems, a PLL generates output clock signals having synchronizing rising edges (or falling edges) with an input reference clock signal.
Conventionally, the PLL includes a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a voltage controlled oscillator (VCO), and a frequency divider. The PFD compares the phase of an input signal with the phase of a frequency division signal fed back from the frequency divider so as to generate a control signal and provide the same to the CP. In accordance with the control signal, the CP determines if an output voltage of the CP is increased or decreased. The LPF is capable of filtering high frequency spurs of the output voltage of the CP. The VCO receives the filtered output voltage from the CP so as to generate an output signal. The frequency divider divides the frequency of the output signal from the VCO to generate the frequency division signal and transmits the frequency division output signal to the PFD.
Quantization errors inevitably occur when a fractional frequency division is performed by an integer frequency divider. FIG. 1 is a schematic view illustrating errors occurring when the integer frequency divider (e.g. dividing by 4 or 5) is employed to perform the fractional frequency division (e.g. dividing by 4.5).
If the quantization error is pushed to high frequency side and then suppressed by the LPF, spur suppression can be desirably accomplished. However, a tradeoff is required between a bandwidth range and the capacity of spur suppression.
Currently, several conventional techniques using frequency multipliers and modulators (for example, a delta-sigma modulation (DSM)) have been developed to reduce the quantization errors. FIGS. 2a and 2b depict two conventional PLLs with use of the frequency multipliers and the modulators for error reduction.
Please refer to FIG. 2a. The first conventional PLL includes a frequency multiplier 201, a PFD 202, a CP 203, an LPF 204, a VCO 205, a frequency divider 206 and a modulator 207. Through the first conventional PLL, quantization errors are pushed to high frequency side, and a wider operation bandwidth is acquired, while the frequency resolution is reduced.
Please refer to FIG. 2b. The second conventional PLL includes a frequency multiplier 201′, a PFD 202′, a CP 203′, an LPF 204′, a VCO 205′, a frequency divider 206′, and a modulator 207′. A disadvantage of the second conventional PLL lies in that the output signal of the frequency divider 206′ does not have 50% duty cycles, and an additional duty cycle correction circuit is necessitated. Moreover, modulus errors may occur.